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<language name="VHDL" version="1.08" kateversion="2.3" section="Hardware" extensions="*.vhdl;*.vhd" mimetype="text/x-vhdl" author="Rocky Scaletta (rocky@purdue.edu), Stefan Endrullis (stefan@endrullis.de), Jan Michel (jan@mueschelsoft.de)">
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      <item> file </item>
      <item> package </item>
      <item> library </item>
      <item> use </item>
<!--
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      <item> architecture </item>
      <item> of </item>
      <item> configuration </item>
-->
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      <item> alias </item>
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      <item> block </item>
      <item> body </item>
      <item> bus </item>
      <item> component </item>
      <item> constant </item>
      <item> disconnect </item>
      <item> downto </item>
      <item> end </item>
      <item> exit </item>
      <item> function </item>
      <item> generate </item>
      <item> generic </item>
      <item> group </item>
      <item> guarded </item>
      <item> impure </item>
      <item> inertial </item>
      <item> is </item>
      <item> label </item>
      <item> linkage </item>
      <item> literal </item>
      <item> map </item>
      <item> new </item>
      <item> next </item>
      <item> null </item>
      <item> on </item>
      <item> open </item>
      <item> others </item>
      <item> port </item>
      <item> postponed </item>
      <item> procedure </item>
      <item> process </item>
      <item> pure </item>
      <item> range </item>
      <item> record </item>
      <item> register </item>
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      <item> report </item>
      <item> return </item>
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      <item> severity </item>
      <item> signal </item>
      <item> shared </item>
      <item> subtype </item>
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      <item> to </item>
      <item> transport </item>
      <item> type </item>
      <item> unaffected </item>
      <item> units </item>
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      <item> variable </item>
      <item> wait </item>
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      <item> with </item>
      <item> note </item>
      <item> warning </item>
      <item> error </item>
      <item> failure </item>
      <item> in </item>
      <item> inout </item>
      <item> out </item>
      <item> buffer </item>
      <item> and </item>
      <item> or </item>
      <item> xor </item>
      <item> not </item>
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    <list name="if">
      <item> else </item>
      <item> elsif </item>
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    <list name="forOrWhile">
      <item> loop </item>
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    <list name="directions">
      <item> in </item>
      <item> inout </item>
      <item> out </item>
      <item> buffer </item>
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    <list name="signals">
      <item> signal </item>
      <item> variable </item>
      <item> constant </item>
      <item> type </item>      
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 <!--   <list name="logics">
      <item> and </item>
      <item> or </item>
      <item> xor </item>
      <item> not </item>
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    <list name="rangeDirection">
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      <item> downto </item>
    </list>-->
    
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      <item> character </item>
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      <item> integer </item>
      <item> real </item>
      <item> time </item>
      <item> string </item>
      <item> severity_level </item>
      <item> positive </item>
      <item> natural </item>
      <item> signed </item>
      <item> unsigned </item>
      <item> line </item>
      <item> text </item>
      <item> std_logic </item>
      <item> std_logic_vector </item>
      <item> std_ulogic </item>
      <item> std_ulogic_vector </item>
      <item> qsim_state </item>
      <item> qsim_state_vector </item>
      <item> qsim_12state </item>
      <item> qsim_12state_vector </item>
      <item> qsim_strength </item>
      <item> mux_bit </item>
      <item> mux_vector </item>
      <item> reg_bit </item>
      <item> reg_vector </item>
      <item> wor_bit </item>
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    <comments>
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    <keywords casesensitive="0" />
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</language>