Short Introduction into IEEE 1394

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# Chapter 2. Short Introduction into IEEE 1394

IEEE 1394 in fact defines two types of hardware implementations for this bus system, cable and backplane. The only one described here and supported by the Linux subsystem is the cable implementation. Most people not familiar with the standard probably don't even know that there is something else than the 1394 cable specification.

If you are familiar with CSR architectures (as defined in --FIXME--), then you already know most of 1394, which is a CSR implementation.

# Bus Structure

The basic data structures defined in the standard and used in this document are the quadlet (32 bit quantity) and the octlet (64 bit quantity) and blocks (any quantity of bytes). The bus byte ordering is big endian. A transmission can be sent at one of multiple possible speeds, from the slowest 100 Mbit/s over 200 and 400 Mbit/s up to 3.2 Gbit/s in the future (these speeds are also referred to as S100, S200, ...).

A 1394 bus consists of up to 64 nodes (with multiple buses possibly being connected, but that is outside of the scope of this document and not completely standardized yet), each having a local address space with 48 bit wide addressing. Each node is addressed with a 16 bit address, which is further divided into a 10 bit bus ID and a 6 bit local node ID. The highest value for both is a special value. Bus ID equal to 1023 means "local bus" (the bus the node is connected to), node ID equal to 63 means "all nodes" (broadcast).

The whole bus can thus be seen as a linear 64 bit address space by concatenating the node address (most significant bits) and and node address (least significant bits). libraw1394 treats them separately in function arguments to save the application some fiddling with the bits. The node IDs are completely dynamic and determined during the bus reset.

Unlike other buses there aren't many transactions or commands defined, higher level commands are defined in terms of addresses accessed instead of separate transaction types (comparable to memory mapped registers in hardware). The 1394 transactions are:

- read (quadlets and blocks)

- write (quadlets and blocks)

- lock (some atomic modifications)

There is also the isochronous transaction (the above three are called asynchronous transactions), which is a broadcast stream with guaranteed bandwidth. It doesn't contain any address but is distinguished by a 6 bit channel number.

The bus view is only logical, physically it consists of many point-to-point connections between nodes with every node forwarding data it receives to every other port which is capable of the speed the transaction is sent at (thus a S200 node in the path between two S400 nodes would limit their communication speed to S200). It forms a tree structure with all but one node having a parent and a number of children. One node is the root node and has no parents.

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